A Local Area Network (LAN) utilizes a clock recovery scheme to extract a clock signal from the data transmitted between stations over the network. The recovered clock signal is then used to synchronize the operations performed on the incoming data, e.g., sampling and decoding of the data.
FIG. 1 shows the primary functional components of a transmitting station 11 and a receiving station 13 of a LAN 10 that are involved in the clock recovery function during the transmission and reception of data. As shown in FIG. 1, the MAC (media access control) layer 12 of the transmitting station (or node) 11 provides data to the PHY (physical) layer 14. The PHY layer 14 encodes the data using a conventional 4B/5B protocol, serializes it, and then scrambles the data stream.
While the 4B/5B encoding insures at least one transition per 5 bits, the scrambling of the data stream reduces the transition density such that there may be as many as 60 consecutive ones or zeros. The phase locked loop (PLL) used to control the sampling of the data must, therefore, be able to keep tracking the frequency difference between the transmitting station 11 and the receiving stations 13 (which is used to control the adaptation of the voltage controlled oscillator which is part of the loop) in the absence of transitions on the incoming data stream. Therefore, a 2nd order loop transfer function for a voltage controlled oscillator (VCO) or frequency controlled oscillator (FCO) type loop (phase error, frequency adjust) is required, or a 1st order loop transfer function for a phase error/phase adjust control system.
With reference to FIG. 1, the scrambled data is passed to TP-PMD 16 at 125 mb/sec. twisted-pair, physical medium dependent (TP-PMD) 16 then encodes the data using MLT3 encoding and drives the twisted pair 18 which forms the transmission medium for the data. MLT3 encoding takes the binary coded message and drives the cable using three output levels in such a way that the power spectral density contains less energy at high frequencies.
At the receive end of twisted pair 18, the TP-PMD 20 of the receiving station 13 does adaptive equalization of the incoming data stream (to minimize the effects of the channel on the signal), MLT3 decoding, and passes the binary 125 mb/sec signal to the receiver PHY layer 22. The receive side of PHY layer 22 must recover a 125 Mhz clock from this data stream, use this clock to sample the data, unscramble the data, convert 4B/5B to nibble wide data, and provide a nibble wide data stream with a 25 Mhz clock to the MAC layer 24 of receiving station 13.
Typically, the stations (or nodes) of such a network will have TP-PMDs and PHYs that can operate at data rates of both 10 Mhz and 100 Mhz. Prior art solutions have used a separate clock recovery channel for each of the 10 and 100 Mhz data rates. This necessitates some duplication of the architecture in both a functional and a structural sense, with the result that excessive surface area and power are consumed.
The data presented by TP-PMD 20 has 1.3 ns p-p DCD (duty cycle distortion) jitter, 2.0 ns peak to peak DDJ (data dependent) jitter, and 2.7 ns p-p gaussian jitter. This leaves a 2 ns jitter-free segment out of an 8 ns window. The clock recovery circuit must be able to ignore the jitter and track only the frequency difference between the transmitting station 11 and the receiving station 13. By adapting the tracking behavior of the clock recovery circuit to the phase difference between the signals, the frequency at which the receiving station 13 samples the transmitted signal can be synchronized to the frequency and phase at which the signal was originally transmitted. The maximum frequency difference between the stations is 100 ppm, so a narrow band phase-locked-loop (PLL) suffices. As noted, the PLL must also be able to keep tracking this frequency difference in the absence of transitions on the incoming data stream, which may contain as many as 60 consecutive ones or zeros. The 10BT jitter specification requires recovering clock and data from a data stream with 36 ns p-p fixed jitter, 36 ns p-p random jitter, or any combination of fixed and random jitter adding up to 36 ns p-p (The 10 mb p-p jitter window is 50 ns; therefore, the jitter is taking 36 ns out of this 50 ns, leaving a 14 ns eye.).
A typical mixed signal (dual channel) approach to clock recovery uses a digital three state frequency/phase detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), and a divide by N circuit for each channel.
FIG. 2 shows the primary functional components of a clock recovery circuit 50 incorporating a VCO based phase-locked loop which may be used for each channel of a dual channel clock recovery circuit. The inputs to phase/frequency comparator 52 are the data stream 54, labelled "rx_data" in FIG. 2, and a recovered clock signal labelled "RXC", which represents a control signal output by VCO 56. The recovered clock signal RXC is used to sample the incoming data stream rx_data and is brought into phase alignment with the incoming data stream by the action of the illustrated feedback loop 50. The frequency/phase error between the two inputs to comparator 52 creates a pulse-width modulated pump-up (pumpup) stream and pump-down (pumpdn) stream which are provided as the inputs to charge pump 58. Charge pump 58 charges up when the pumpup pulse is high, and charges down when the pumpdn pulse is high. The output voltage of charge pump 58 is filtered by a loop filter 60, and is typically input to a level translating and slope reversing circuit (not shown) which controls the bias voltage of VCO 56. The output of VCO 56 is provided as an input to a divide-by-N circuit (not shown). The output of the divide-by-N circuit is the RXC input to phase comparator 52.
FIG. 3 shows the analog equivalent of an optimal loop filter 70 suitable for use as the loop filter 60 of the FIG. 2 clock recovery circuit 50. For a clock recovery circuit that is designed to track a frequency difference while rejecting noise present on the input signal, filter 70 is an optimal filter. This type of filter results in a second order loop transfer function for phase compare, frequency adjust type loops, and a first order loop transfer function for phase compare, phase adjust (phase picker) type loops. Integrator 72 of loop filter 70 provides a high DC gain, which means that the filter can track phase variations that change slowly with time with a small amount of error. With resistor 74 and resistor 76 chosen to give low proportional gain, the filter will not track phase variations that change rapidly with time. Since a small frequency difference between stations corresponds to a slow change in phase, d.phi./dt (where .phi. is the phase of the signal), and noise present on the input signal has a fast d.phi./dt, filter 70 works well for narrow band (small .DELTA.f) clock recovery.
However, there are several problems encountered when using the circuit illustrated in FIGS. 2 and 3. These include: (1) the gain of the loop 50 depends on process, voltage, and temperature (PVT); (2) the 3-state phase/frequency detector 52 only looks at the rising edge of the input signal and, therefore, it is not possible to lock to the center of a bimodal jitter distribution; (3) the loop filter 60 takes up considerable silicon surface area and does not shrink with feature size; and (4) multiple VCO's on a single substrate can cause injection of one VCO's clock into another VCO.
Another approach to clock recovery is to use a frequency controlled oscillator (FCO), charge pump, and digital loop filter. This approach utilizes a phase detector that can lock to the center of a bimodal jitter distribution, but still uses a charge pump. The digital loop filter creates a pulse density modulated pulse stream to the FCO, where the pulse density modulates the frequency of the FCO. The disadvantages of this approach are: (1) the gain still depends on PVT and (2) the silicon surface area is still large compared to a completely digital approach.
Yet another approach to clock recovery is to use a phase picker architecture. FIG. 4 shows the primary functional components of a clock recovery circuit 80 incorporating a phase picker based phase-locked loop which may be used for both channels of a dual channel clock recovery circuit. A phase picker implements a clock recovery loop using a phase comparator 82 to determine the phase error between the comparator inputs, with the output of the phase comparator directly selecting a new phase of the recovered clock signal by using a phase multiplexer 84. The inputs to phase multiplexer 84 are N phases P1-PN of the signal RXC, which are provided by a clock generation module (not shown). The signals output by phase comparator 82 control the operation of phase multiplexer 84 to select one of the N phases P1-Pn.
The inputs to phase comparator 82 are the incoming data stream 54, labelled "rx_data" in FIG. 4, and a signal labelled "RXC 86", which is the clock phase selected by phase multiplexer 84. As before, the RXC signal 86 is used to control the sampling of the data and is brought into phase alignment with the data by the action of the illustrated feedback loop 80.
One limitation of the phase picker architecture is that the amount of attenuation of the proportional control is limited by the phase step resolution of the phase multiplexer. For example, if the resolution is 1 ns, then a leading phase error (RXC leads the input data) would always adjust the phase by retarding RXC by at least 1 ns.
Another limitation of such clock recovery circuits is that the architecture only allows proportional control; there is no means for adding integral control. This is a disadvantage because integral control is desirable to obtain high DC gain and, hence, good tracking behavior.
Finally, another approach to clock recovery i s to use a full digital signal processing (DSP) solution. This requires sampling at least at the Nyquist rate, and running the full DSP algorithm at this rate. Therefore, this approach is very power intensive.
What is desired is an apparatus for recovering a clock signal from a transmitted data stream using a single clock recovery channel capable of operating at both 10 mb/sec and 100 mb/sec data rates. This reduces the surface area and power required to extract a clock signal from the data transmitted between two stations or nodes of a local area network.